1. Field of the Invention
The present invention relates to a method for fabricating semiconductor devices, and more particularly to a method for fabricating capacitors with a structure having hemispherical grains, thereby being capable of achieving an increase in the minimum capacitance-to-maximum capacitance ratio (hereinafter, referred to as a "Cmin/Cmax" ratio).
2. Description of the Related Art
In a semiconductor memory device, such as a dynamic random access memory (DRAM), including a plurality of memory cells each consisting of one access transistor and one storage capacitor, cell capacitance is important for an improvement in cell memory characteristics in that it serves to improve the read-out ability of the memory device while reducing the soft error rate (SER). However, the recent high integration trend of semiconductor devices inevitably involves a reduction in the cell area per cell, thereby resulting in a reduction in the area occupied by the capacitor. For this reason, it is essentially required to achieve an increase in the capacitance per cell area, in addition to an increase in the integration degree.
Generally, capacitance is proportional to how much area is shared by lower and upper electrode layers. A number of efforts have continuously been made to increase the surface area of the lower electrode layer in a limited space. Most of such efforts are concerned with lower electrode layer structures. By virtue of such efforts, capacitors have been developed from planar capacitor structures, which were initially proposed, up to three-dimensional capacitor structures such as those of stacked capacitors or trenched capacitors. However, attempts to increase capacitance by an improved lower electrode layer structure as mentioned above encounter problems such as a limited design rule and complicated fabrication processes. To this end, proposals have been made to utilize physical properties of the lower electrode layer, thereby achieving an increase in capacitance. Of these proposals, one is disclosed in U.S. Pat. No. 5,385,863, wherein hemispherical grains (HSG) are formed on the surface of a lower electrode layer, thereby increasing the surface area of the lower electrode layer. In accordance with this method, an amorphous silicon layer is formed over a wafer using a low pressure chemical vapor deposition (LPCVD) process. Phosphorous (P) ions are then implanted in the amorphous silicon layer. Subsequently, the surface of the amorphous silicon layer is cleaned, thereby removing a natural oxide film existing thereon. The resulting wafer is then loaded in a chamber defined in an ultra-high vacuum CVD device. The chamber is maintained at an ultra-high vacuum of 10.sup.-9 Torr. In the chamber, the wafer is heated to a desired temperature ranging from 500.degree. C. to 620.degree. C. Under this condition, source gas such as silane (SiH.sub.4) or disilane (Si.sub.2 H.sub.6) is supplied into the chamber, so that crystal nucleuses are formed on the amorphous silicon layer. This technique is generally called a "crystal seeding process". After the formation of the crystal nucleuses, the resulting wafer is subjected to a thermal treatment in high vacuum. By this thermal treatment, the crystal nucleuses are grown into hemispherical grains. Consequently, the amorphous silicon layer is transformed into a polysilicon layer having an irregular surface.
Now, a conventional method for fabricating capacitors with hemispherical grains will be described in conjunction with FIGS. 1 and 2. The following description will be made only in conjunction with a unit cell.
Referring to FIG. 1, an insulating layer 12 is first formed over a semiconductor substrate 10 formed with a transistor (not shown). The insulating layer 12 is then etched using a photolithography process, thereby forming a contact hole through which an active region, for example, a source region of the transistor, is exposed. An amorphous silicon layer 16 is subsequently deposited over the insulating layer 12 including the contact hole 14 in accordance with an LPCVD process. The amorphous silicon layer 16 is then doped with phosphorous (P) ions. Thereafter, a photoresist film pattern 18, which is to be used for the formation of a lower electrode layer constituting a part of a capacitor, is formed on the amorphous silicon layer 16. Using the photoresist film pattern 18 as an etch mask, the amorphous silicon layer 16 is then dry etched by use of chlorine (Cl.sub.2)-based plasma, so that it is patterned to have a shape corresponding to a desired lower electrode layer shape. As the amorphous silicon layer 16 is dry etched, its side walls are damaged. As a result, an inclined side wall profile is obtained.
As shown in FIG. 2, the photoresist film pattern 18 is then removed, thereby exposing the patterned amorphous silicon layer 16. Subsequently, hemispherical grains 20 are grown over the amorphous silicon layer 16 using a well-known crystal seeding process and thermal treatment process. A subsequent thermal treatment at a temperature of about 800.degree. C. is carried out for the amorphous silicon layer 16, thereby causing the amorphous silicon layer 16 to be transformed into a polysilicon layer as a lower electrode layer. Although not shown, a dielectric layer and an upper electrode layer are then sequentially formed on the lower electrode layer with the hemispherical grains 20, thereby obtaining a capacitor.
FIG. 3 is an enlarged view of one of hemispherical grains 20 shown in FIG. 2. Referring to FIG. 3, it can be found that there is no migration of phosphorous (P) ions 24 to the surface 22 of the hemispherical grain 20. This is because an etch damage of the side walls of the amorphous silicon layer 16, which occurs during the dry etching of the amorphous silicon layer 16, results in an easy crystallization of amorphous silicon during a subsequent growth of hemispherical grains, thereby forming grain boundaries interfering with a migration of the P ions.
When the concentration of the dopant, namely, P ions, at the surfaces 22 of the hemispherical grains 20 decreases, the capacitance of the capacitor varies depending on the direction in which bias is applied to the capacitor, namely, the direction in which electric field is applied to the dielectric layer. This will be described in more detail.
Typically, when data is stored in a capacitor, electrons or holes concentrate on the surface of the lower electrode layer of a capacitor by virtue of electric field generated due to a differential voltage potential across both nodes of the dielectric layer. In particular, where the dielectric layer exhibits a higher potential at the lower node thereof than at the upper node thereof, holes in the lower electrode layer migrate toward the upper electrode layer due to the electric field applied to the dielectric layer. As a result, those holes concentrate on the surface of the lower electrode layer. When the concentration of the dopant at the surfaces of hemispherical grains decreases, carriers in the surface of the lower electrode layer are offset with each other, thereby forming a depletion layer. This depletion layer serves as a parasitic capacitor. Assuming that "Cd" and "Cc" represent the capacitance of such a parasitic capacitor and the capacitance generated by the dielectric layer, respectively, a relationship of Cd&lt;&lt;Cc is established.
Since the upper electrode layer, the parasitic capacitor resulting from the deletion layer, and the capacitor resulting from the dielectric layer, and the lower electrode are coupled together in series, the total capacitance Ct is expressed as follows: ##EQU1##
Taking into consideration the relationship of Cd&lt;&lt;Cc, it can be found from the above equation that a relationship of Ct&lt;Cc is established. This means that the Cmin/Cmax ratio is reduced.
For DRAM products, the minimum capacitance Cmin has a very important meaning. This is because a "high" potential level is used upon storing data of "1". The use of a "high" potential level means that such a "high" potential level is applied to the lower node of the capacitor. In other words, it is meant that the potential of the upper node is higher than that of the lower node. As a result, if the concentration of the dopant at the surfaces of hemispherical grains decreases, the capacitor is then charged in a reduced quantity upon storing data of "1", as compared to the case in which data of "0" is stored. Such asymmetric capacitance results in a degradation in the performance of the entire semiconductor chip.